Electronic Warfare FPGA Engineer

About the role

The Electronic Warfare FPGA Engineer implements high-performance signal processing pipelines for SDR and EW/ESM systems, bridging algorithm development and hardware realization. You turn DSP, radar and EW concepts into deterministic, resource-efficient FPGA architectures while prototyping and validating algorithms in Python. You work with algorithm, RF and embedded/FPGA teams to deliver real-time processing chains from wideband IQ ingestion to detection, parameter extraction and reporting.

Key responsibilities

• Implement FPGA-based DSP pipelines for SDR, ESM and EW systems, translating Python (NumPy/SciPy) and C++ prototypes into synthesizable HDL (VHDL/Verilog/SystemVerilog)
• Optimize fixed-point representations and implement CORDIC, CIC filters, half-band filters, polyphase filter banks, FFT pipelines and high-throughput detection and radar processing
• Implement communications blocks such as synchronization, preamble detection and pilot-based channel estimation
• Design memory-efficient architectures using BRAM, URAM and external DDR, and streaming pipelines with controlled latency
• Implement high-speed interfaces such as Ethernet and PCIe, and work with RFSoC and direct RF sampling architectures
• Debug algorithms in Python, maintain golden reference model validation, use IQ inspection tools and bench-level validation, and develop simulation testbenches
• Use on-chip debug tools (ILA/VIO), collaborate with embedded and software engineers, and take part in design reviews

Required profile

• Bachelor's degree in Electrical Engineering, Computer Engineering or a related field
• 2+ years of professional FPGA development experience in DSP, radar, communications or EW
• Strong foundation in DSP theory, SDR, digital communications, radar signal processing and signal detection theory
• Deep understanding of CFAR and its hardware constraints
• Experience with RF test equipment (spectrum analyzers, signal generators)

Required skills

• Python (NumPy/SciPy) and ability to convert floating-point prototypes to fixed-point HDL
• FPGA memory architectures (BRAM, URAM, DDR) and Ethernet/PCIe data movement
• Preferred: PDW extraction pipelines, GNU Radio, RFSoC, hardware/software co-design, CI/CD for FPGA builds, radar and array signal processing

What we offer

• Competitive salary and a benefits package including health insurance and fuel support
• Ongoing support for candidates enrolled in a master's or doctoral program
• Opportunities for professional growth in a collaborative, innovative environment