Senior AMS Verification Engineer

About the role

Renesas is seeking a Senior AMS Verification Engineer to join its Istanbul team, focusing on analog mixed‑signal verification at both block and full‑chip levels.

Key responsibilities

• Lead verification planning and execution at the block and full‑chip level.
• Work closely with architects and designers to align verification goals with design intent and architectural requirements.
• Drive enhancements in verification methodology while mentoring and supporting team members’ development.
• Develop event‑driven models for analog IC components and verify them.

Required profile

• MSEE with 10+ years or PhD with 7+ years of verification experience.
• Advanced knowledge of SystemVerilog and UVM methodology.
• Understanding of power management and related auxiliary circuitry such as switching converters, linear converters, reference circuitry, bandgaps, data converters, and clock generators.
• Hands‑on experience with verification tools, including simulation, waveform analysis, execution automation, coverage collection, and gate‑level simulations.
• Experience in Event Driven Modelling/Verification is a plus.
• Knowledge of scripting languages (Perl, Python, Tcl) is a plus.
• Fluent in English with clear written and verbal communication, including code documentation.

Required skills

• SystemVerilog
• UVM methodology
• Event‑driven modelling
• Perl
• Python
• Tcl
• Simulation tools
• Waveform analysis
• Coverage collection
• Gate‑level simulation